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1 for more information www.linear.com/ltm8049 typical application features description dual sepic or inverting module dc/dc converter the lt m ? 8049 is a dual sepic/inverting module ? (power module) dc/dc converter. each of the two outputs can be easily configured as a sepic or inverting converter by simply grounding the appropriate output rail. the ltm8049 includes power devices, inductors, control circuitry and passive components. all that is needed to complete the design are input and output caps, and small resistors to set the output voltages and switching frequency. other components may be used to control the soft-start and undervoltage lockout. the ltm8049 is packaged in a thermally enhanced, com - pact ( 15mm 9mm ) over-molded ball grid array (bga) package suitable for automated assembly by standard surface mount equipment. the ltm8049 is available with snpb (bga) or rohs compliant terminal finish. maximum load current vs v in 12v out from 2.7v in to 20v in applications n two complete switch mode power supplies n sepic or inverting topology n wide input voltage range: 2.6v to 20v n 2.5v to 24v or C2.5v to C24v output voltage n 1a at 5v out from 12v in n selectable switching frequency: 200khz to 2.5mhz n power good outputs for event based sequencing n user configurable undervoltage lockout n (e4) rohs compliant package with gold pad finish n low profile 15mm 9mm 2.42mm surface mount bga package n battery powered regulator n local negative voltage regulator n low noise amplifier power all registered trademarks and trademarks are the property of their respective owners. lt m8049 8049fa 1.0 1.5 load current (a) 8049 ta01 ltm8049 130k 8049 ta01a v out1p v out1n v in1 v in (v) run1 rt1 80.6k 1mhz v in 2.7v to 20v v out1 12v v out2 ?12v 4.7f 2 22f 47f sync2 0 clkout1 fbx1 rt2 80.6k 1mhz 143k v out2p v out2n v in2 run2 sync1 5 pins not used: ss1, ss2, pg1, pg2, clkout2, share1, share2 fbx2 10 15 20 0 0.5
2 for more information www.linear.com/ltm8049 pin configuration absolute maximum ratings v inn , runn, pgn ....................................................... 20v syncn, fbxn .............................................................. 5v ssn .......................................................................... 2.5v sharen ...................................................................... 2v v outp (v outn = 0v ) .................................................. 25v v outn (v outp = 0v ) ................................................ C 25v maximum internal temperature ............................ 125 c maximum solder temperature .............................. 260 c storage temperature .............................. C 55 c to 125 c (note 1) 9 4 4 4 t jmax = 125c, ja = 16.2c/w, jb = 3.8c/w, jctop = 8.8c/w, jcbottom = 3.8c/w, jcboard = 4.6c/w, weight = 0.8g, values determined per jedec 51-9, 51-12 order information part number pad or ball finish part marking* package type msl rating tempera ture range (see note 2) device finish code ltm8049ey#pbf sac305 (rohs) ltm8049y e1 bga 3 C40c to 125c ltm8049iy#pbf ltm8049iy snpb (63/37) ltm8049 e0 * device temperature grade is indicated by a label on the shipping container . ? pad or ball finish code is per ipc/jedec j-std-609. ? t erminal finish part marking: www.linear.com/leadfree ? this product is not recommended for second side reflow . for more information, go to www.linear.com/bga-assy ? recommended bga pcb assembly and manufacturing procedures : www.linear.com/bga-assy ? bga package and t ray drawings: www.linear.com/packaging ? this product is moisture sensitive. for more information, go to : www.linear.com/bga-assy http://www.linear.com/product/ltm8049#orderinfo lt m8049 8049fa
3 for more information www.linear.com/ltm8049 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm8049e is guaranteed to meet performance specifications from 0c to 125c. specifications over the C40c to 125c internal temperature range are assured by design, characterization and correlation with statistical process controls. ltm8049i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: this module regulator includes overtemperature protection that is intended to protect the device during momentary overload conditions. internal temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum internal operating junction temperature may impair device reliability. note 4: clkoutn is intended to drive other circuitry. do not apply a positive or negative voltage or current source to clkout, otherwise permanent damage may occur. note 5: the duty cycle of clkout2 is dependent upon the internal temperature. see the applications information section for more details. the l denotes the specifications which apply over the specified operating temperature range (notes 2, 3), otherwise specifications are at t a = 25c. run = 2v unless otherwise specified. parameter conditions min typ max units minimum input operating voltage l 2.6 v positive output dc voltage i out = 50ma, r fb = 15.4k, v outn grounded i out = 50ma, r fb = 274k, v outn grounded 2.5 24 v v negative output dc v oltage i out = 50ma, r fb = 30.1k, v outp grounded i out = 50ma, r fb = 287k, v outp grounded C2.5 C24 v v maximum continuous output dc current v in = 12v, v out = 5v or C5v v in = 12v, v out = 24 or C24v 1 0.25 a a v in quiescent current v run = 0v v run = 2v, no load 0 10 2 a ma line regulation 4 v in 20v, i out = 0.6a 0.1 % load regulation 0 i out 1a 0.3 % switching frequency r t = 31.6k r t = 412k l l 2100 160 2500 200 2900 240 khz khz v oltage at fbx pin positive output negative output l l 1.185 2 1.204 7 1.22 16 v mv current into fbx pin positive output negative output l l 81 81 83.3 83.3 85.6 85.6 a a run pin threshold v oltage run pin rising run pin falling 1.21 1.31 1.27 1.4 v v run pin current v run = 3v v run = 1.3v v run = 0v 10.1 45 12.1 0 65 14.1 0.1 a a a ss sour cing current ss = 0v 5.7 8.8 11.7 a synchronization frequency range 200 2500 khz sync input low threshold 0.4 v sync input high threshold 1.3 v clkout1 duty cycle (note 5) 50 % clkout output voltage (low) 2k pull-up to 2v 0.2 v clkout output voltage (high) 2k pull-down to gnd 1.9 v pg threshold for positive feedback voltage fbx rising 1.09 1.2 v pg threshold for negative feedback voltage fbx falling 20 120 mv pg output voltage low 100a into pg, fbx = 1v 150 mv pg leakage current pg = 20v, run = 0v 1 a lt m8049 8049fa
4 for more information www.linear.com/ltm8049 typical performance characteristics efficiency, v out 2.5v efficiency, v out 3.3v efficiency, v out 5v efficiency, v out 8v efficiency, v out 12v efficiency, v out 15v efficiency, v out 18v efficiency, v out 24v input vs load current, v out 2.5v lt m8049 8049fa 45 efficiency (%) 8049 g03 5v in 12v in 16v in load current (a) 0 0.25 0.50 0.75 55 1 55 65 75 85 efficiency (%) 8049 g06 5v in 8v in load current (a) 65 0 0.5 1 1.5 2 0 0.5 1.0 1.5 2.0 75 2.5 input current (a) 8049 g09 efficiency (%) 8049 g01 5v in 12v in 16v in load current (a) 5v in 0 0.5 1 1.5 55 65 75 85 efficiency (%) 8049 g04 8v in 5v in 12v in 16v in load current (a) 0 0.20 0.40 0.60 0.80 55 load current (a) 65 75 85 efficiency (%) 8049 g07 5v in 12v in load current (a) 0 0.5 0 1 1.5 2 45 55 65 75 efficiency (%) 8049 g02 5v in 0.5 12v in 16v in load current (a) 0 0.50 1 1.50 55 65 75 1 85 efficiency (%) 8049 g05 5v in 12v in 16v in load current (a) 0 0.2 0.4 1.5 0.6 55 65 75 85 efficiency (%) 8049 g08 5v in 12v in 15v in 2 load current (a) 0 0.5 1 1.5 2 50 60 70 80
5 for more information www.linear.com/ltm8049 typical performance characteristics input vs load current, v out 3.3v input vs load current, v out 5v input vs load current, v out 8v input vs load current, v out 12v input vs load current, v out 15v input vs load current, v out 18v input vs load current, v out 24v maximum load current vs v in maximum load current vs v in lt m8049 8049fa 0 8049 g17 5v in 12v in 16v in load current (a) 0 0.5 0.5 1 1.5 0 1.0 2.0 3.0 input current (a) 8049 g12 5v in 1.0 12v in 16v in load current (a) 0 0.2 0.4 0.6 0.8 1.5 0 1.0 2.0 3.0 input current (a) 8049 g15 8v out 12v out 15v out v in (v) 2.0 0 5 10 15 20 0 0.5 1.0 1.5 2.0 2.5 load current (a) 8049 g18 per channel input current (a) 8049 g10 5v in 5v in 12v in 16v in load current (a) 0 0.50 1 1.50 0 12v in 1.0 2.0 3.0 input current (a) 8049 g13 5v in 12v in 16v load current (a) in load current (a) 0 0.2 0.4 0.6 0 1.0 2.0 3.0 0 input current (a) 8049 g16 5v in 12v in 15v in load current (a) 0 0.5 1 1.5 0.5 2 0 1.0 2.0 3.0 input current (a) 8049 g11 5v in 12v 1 in 16v in load current (a) 0 0.25 0.50 0.75 1 0 1.5 1.0 2.0 3.0 input current (a) 8049 g14 2.5v out 3.3v out 5v out v in (v) 0 2 5 10 15 0 0.5 1.0 1.5 2.0 load current (a) per channel
6 for more information www.linear.com/ltm8049 typical performance characteristics maximum load current vs v in derating curve, v out 2.5v out derating curve, v out 3.3v out derating curve, v out 5v out derating curve, v out 8v out derating curve, v out 12v out derating curve, v out 15v out derating curve, v out 18v out derating curve, v out 24v out lt m8049 8049fa 0 0.50 0.75 1.00 output current (a) 8049 g26 ambient temperature ( c) 0 lfm 5v in 12v in ambient temperature ( c) 0.25 0 25 50 75 100 125 0 0.50 1.00 1.50 0.50 2.00 output current (a) 8049 g21 0 lfm 5v in 12v in 16v in 0 25 50 0.75 75 100 125 0 0.50 1.00 1.50 output current (a) 8049 g24 ambient temperature ( c) 1.00 0 lfm 5v in 12v in 16v in 0 25 50 75 100 125 load current (a) 0 0.25 0.50 0.75 output current (a) 8049 g27 ambient temperature ( c) 8049 g19 per channel 0 lfm 5v in 18v out 12v in 15v in 0 25 50 75 100 125 0 0.50 24v out 1.00 1.50 2.00 output current (a) 8049 g22 ambient temperature ( c) 0 lfm 5v in 12v in 16v in v in (v) 0 25 50 75 100 125 0 0.25 0.50 0.75 0 1.00 output current (a) 8049 g25 ambient temperature ( c) 0lfm 5v in 8v in 0 25 50 5 75 100 125 0 0.50 1.00 1.50 2.00 output current (a) 8049 g20 10 ambient temperature ( c) 0 lfm 5v in 12v in 16v in 0 25 50 75 100 15 125 0 0.50 1.00 1.50 output current (a) 8049 g23 ambient temperature ( c) 0 lfm 5v in 20 12v in 16v in 0 25 50 75 100 125 0 0.25
7 for more information www.linear.com/ltm8049 typical performance characteristics clkout2 duty cycle vs temperature output ripple, dc2244a board 800ma load, 12v in measured across c5, c6 pin functions gnd (bank 1): tie these gnd pins to a local ground plane below the ltm8049 and the circuit components. gnd must be connected either to v outp or v outn for proper operation. in most applications, the bulk of the heat flow out of the ltm8049 is through these pads, so the printed circuit design has a large impact on the thermal performance of the part. see the pcb layout and thermal considerations sections for more details. return the feedback divider (rfb) to this net. v in1 , v in2 (banks 2, 3): the v inn pins supply current to the ltm8049 s internal regulator and to the internal power switch. this pin must be locally bypassed with an external, low esr capacitor. v out1p , v out2p (banks 4, 5): v outnp is the positive out - put of the ltm8049. apply an external capacitor between v outnp and v outnn . tie this net to gnd to configure the lmt8049 as a negative output inverting regulator. v out1n , v out2n (banks 6, 7): v outnn is the negative out- put of the ltm8049. apply an external capacitor between v outnp and v outnn . tie this net to gnd to configure the ltm8049 as a positive output sepic regulator. run1 , ru n2 (pins b7, k7): these pins are used to enable/ disable the chip and restart the soft-start sequence. drive below 1.21v to stop the ltm8049 from switching. drive above 1.4v to activate the device and restart the soft-start sequence. do not float this pin. rt1, rt2 (pins e7, g7): the rtn pins are used to program the switching frequency of the ltm8049 by connecting a resistor from this pin to ground. the switching frequency of the ltm8049 is determined by the equation rtn = (81.6/f osc )-1, where the f osc is the switching frequency in mhz. this pin must have a resistor to gnd. do not apply a voltage to this pin. ss1, ss2 (pins c7, j7): connect a soft-start capacitor from this pin to gnd. upon start-up, the ssn pins will be charged by an internal current source to about 2v. sync1, sync2 (pins d7, h7): to synchronize the switch - ing frequency to an outside clock, simply drive this pin with a clock signal. the high voltage level of the clock needs to exceed 1.3v, and the low level must be less than 0.4v. drive this pin to less than 0.4v to revert to the internal free running clock. ground these pins if synchronization is not required. see the applications information section for more information. lt m8049 8049fa 100 125 20 40 60 80 duty cycle (%) 8049 g28 500ns/div 12v out f sw = 1mhz 50mv/div ?12v out 20mv/div 8049 g29 temperature (c) ?50 ?25 0 25 50 75
8 for more information www.linear.com/ltm8049 pin functions fbx1, fbx2 (pins c1, j1): if configured as a sepic, the ltm8049 regulates its fbx pin to 1.204v. apply a resis - tor between fbx and v outp . its value should be r fb = [(v outp C 1.204)/0.0833]k. if the ltm8049 is configured as an inverting converter, the ltm8049 regulates the fbx pin to 7mv. apply a resistor between fbx and v outn of value r fb = [(|v outn | + 0.007)/0.0833]k. the ltm8049 features frequency foldback to protect the power switches during a fault or output current overload. during start-up, frequency foldback also limits the current the ltm8049 delivers to the load. the user must evaluate the start-up behavior of the ltm8049 to ensure that it properly pow - ers up the load. p g1, pg2 (pins d6, h6): these active high pins indicates that the fbn pin voltage for the corresponding channel is within 4% of its regulation voltage these open drain outputs requires a pull-up resistor to indicate power good. also, the status of these pins is valid only when run > 1.4v and v in > 2.6v. clkout1, clkout2 (pins e6, g6): use these pins to synchronize devices to either channel of the ltm8049. these pins oscillate at the same frequency as the ltm8049 internal oscillator or, if active, the sync pin. the clkout1 signal is about 180 out of phase with the oscillator of channel 1 and duty cycle is about 50%. the clkout2 signal is in phase with the internal oscillator of channel 2 and its duty cycle varies linearly with the internal temperature of the ltm8049 . please refer to the applications information section for detailed information on using clkout2 as an indication of the ltm8049 internal temperature. do not apply a voltage to this pin or use this pin to drive capaci - tive loads greater than 120pf. sha re1 , 2 (pins f3, f4): connect these pins together if the two outputs of the ltm8049 are paralleled. otherwise, leave these pins floating. lt m8049 8049fa
9 for more information www.linear.com/ltm8049 block diagram lt m8049 8049fa 2.2f v in1 run1 rt1 share1 sync1 fbx1 pg1 clkout1 4.7h controller note: channel 1. channel 2 is functional identical, except for the clkout2 vs temperature behavior. please see the pin description and applications information sections for details. 8049 bd gnd v out1p v out1n 4.7h 0.1f
10 for more information www.linear.com/ltm8049 operation the ltm8049 contains two stand-alone switching dc/ dc converters; either one may be configured as a sepic (single-ended primary inductance converter) or inverting power supply simply by tying v outn or v outp to gnd, respectively. it accepts an input voltage up to 20vdc. the output is adjustable between 2.5v and 24v for the sepic, and between C2.5v and C24v for the inverting configura - tion. the ltm8049 can provide 1.5a at v in = 12v when v out = 5v or C5v at ambient room temperature. as shown in the block diagram, the ltm8049 contains a current mode controller, power switching element, power coupled inductor, power schottky diode and a modest amount of input and output capacitance. the ltm8049 is a fixed frequency pwm regulator. the ltm8049 switching can free run by applying a resistor to the rt pin or synchronize to an external source at a frequency between 200khz and 2.5mhz . to synchronize to an external source, drive a valid signal source into the sync pin. see synchronization in the applications section for more details. for most applications, the design process is straight forward, summarized as follows: 1. look at t able 1 and find the row that has the desired input range and output voltage. 2. apply the recommended c in , c out , r adj and r t values. while these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. bear in mind that the maximum output current is limited by junction tempera - ture, the relationship between the input and output voltage magnitude and polarity and other factors. please refer to the graphs in the t ypical performance characteristics section for guidance. table 1 gives the recommended component values and configuration for a single channel. each channel may be configured independently. the maximum frequency (and attendant r t value) at which the ltm8049 should be al - lowed to switch is given in table 1 in the f max column, while the recommended frequency (and r t value) for the ltm8049 also features run and ss pins to control the start-up behavior of the device. the run pin may also be used to implement an accurate undervoltage lockout function by applying a resistor network to the run pin. the ltm8049 features frequency foldback to protect the power switches during a fault or output current overload. during start-up, frequency foldback also limits the current the ltm8049 delivers to the load. the user must evaluate the start-up behavior of the ltm8049 to ensure that it properly powers up the load. the ltm8049 is equipped with a thermal shutdown to protect the device during momentary overload conditions. it is set above the 125c absolute maximum internal tem - perature rating to avoid interfering with normal specified operation, so internal device temperatures will exceed the absolute maximum rating when the overtemperature protection is active. therefore, continuous or repeated activation of the thermal shutdown may impair device reliability . optimal efficiency over the given input condition is given in the f optimal column. running the ltm8049 faster than the recommended frequency may reduce the usable input voltage range. capacitor selection considerations the c in and c out capacitor values in table 1 are the minimum recommended values for the associated oper - ating conditions. applying capacitor values below those indicated in t able 1 is not recommended, and may result in undesirable operation. using larger values is generally acceptable, and can yield improved dynamic response, if it is necessary. again, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. ceramic capacitors are small, robust and have very low esr. however, not all ceramic capacitors are suitable. x5r and x7r types are stable over temperature and ap - plied voltage and give dependable service. other types, including y5v and z5u have ver y large temperature and voltage coefficients of capacitance. in an application applications information lt m8049 8049fa
11 for more information www.linear.com/ltm8049 applications information circuit they may have only a small fraction of their nominal capacitance resulting in much higher output voltage ripple than expected. a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the ltm8049. a ceramic input capacitor combined with trace or cable inductance forms a high q (underdamped) tank circuit. if the ltm8049 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possi - bly exceeding the devices rating. this situation is easily avoided ; see the hot-plugging safely section. programming switching frequency the ltm8049 has an operational switching frequency range between 200khz and 2.5mhz . the free running frequency is programmed with an external resistor from the rt pin to ground. do not leave this pin open under any condition. when the sync pin is driven low (<0.4v), the frequency of operation is set by a resistor from rt to ground. the r t value is calculated by the following equation: r t = 81.6 f osc C 1, where f osc is in mhz and r t is in k ? switching frequency trade-offs it is recommended that the user apply the optimal r t value given in table 1 for the corresponding input and output operating condition. system level or other considerations, however, may necessitate another operating frequency. while the ltm8049 is flexible enough to accommodate a wide range of operating frequencies, a haphazardly chosen one may result in undesirable operation under certain operating or fault conditions. a frequency that is too high can reduce efficiency, reduce the usable input voltage range, generate excessive heat or even damage the ltm8049 in some fault conditions. a frequency that is too low can result in a final design that has too much output ripple or too large of an output capacitor. note that the maximum output current vs input voltage curves given in the typical characteristics section are for the recommended operating conditions in table 1. using a different operating frequency may result in a different maximum output current. table 1. recommended component values and configuration (t a = 25c) v in range (v) v out (v) c in c out r fb () f optimal r toptimal () f max r tmin () 2.6v to 11.5v 2.5v 4.7f 25v 0603 x5r 100f 4v 0805 x5r 15.4k 600khz 137k 2mhz 38.3k 2.6v to 9.5v C2.5v 4.7f 25v 0603 x5r 100f 4v 0805 x5r + 47f 6.3v 0805 x5r 30.1k 600khz 137k 2mhz 38.3k 2.6v to 18v 3.3v 4.7f 25v 0603 x5r 100f 4v 0805 x5r 25.5k 650khz 124k 2.3mhz 33.2k 2.6v to 12v C3.3v 4.7f 25v 0603 x5r 100f 4v 0805 x5r + 47f 6.3v 0805 x5r 39.2k 650khz 124k 2.3mhz 33.2k 2.7v to 20v 5v 4.7f 25v 0603 x5r 47f 6.3v 0805 x5r 45.3k 750k 107k 2.5mhz 31.6k 2.7v to 15v C5v 4.7f 25v 0603 x5r 100f 6.3v 1206 x5r + 47f 10v 1206 x5r 60.4k 750k 107k 2.5mhz 31.6k 2.7v to 20v 8v 4.7f 25v 0603 x5r 22f 10v 1206 x5r 82.5k 1mhz 80.6k 2.5mhz 31.6k 2.7 to 18.5v C8v 4.7f 25v 0603 x5r 2x 47f 10v 1206 x5r 95.3k 1mhz 80.6k 2.5mhz 31.6k 2.7v to 20v 12v 4.7f 25v 0603 x5r 22f 16v 1210 x5r 130k 1mhz 80.6k 2.5mhz 31.6k 2.7v to 20v C12v 4.7f 25v 0603 x5r 47f 16v 1210 x5r 143k 1mhz 80.6k 2.5mhz 31.6k 2.7v to 20v 15v 4.7f 25v 0603 x5r 22f 16v 1210 x5r 165k 1.1mhz 73.2k 1.9mhz 41.2k 2.7v to 20v C15v 4.7f 25v 0603 x5r 47f 16v 1210 x5r 178k 1.1mhz 73.2k 1.9mhz 41.2k 3v to 20v 18v 4.7f 25v 0603 x5r 22f 16v 1210 x7r 200k 1.5mhz 53.6k 1.8mhz 45.3k 3v to 20v C18v 4.7f 25v 0603 x5r 22f 16v 1210 x7r 215k 1.5mhz 53.6k 1.8mhz 45.3k 3.7v to 18v 24v 4.7f 25v 0603 x5r 22f 25v 1206 x5r 274k 1.5mhz 53.6k 1.8mhz 45.3k 3.7v to 18v C24v 4.7f 25v 0603 x5r 22f 25v 1206 x5r 287k 1.5mhz 53.6k 1.8mhz 45.3k note: an input bulk capacitor is required. lt m8049 8049fa
12 for more information www.linear.com/ltm8049 soft-start the soft-start circuitry provides for a gradual ramp-up of the switch current in each channel. when the channel is enabled, the external ss capacitor is first discharged. this resets the state of the logic circuits in the channel. then an integrated resistor pulls the channel s ss pin to about 1.8v. the ltm8049 has a built-in soft-start characteristic, but a slower ramp rate may be implemented by adding capacitance to the ss pin. typical values are between 0.1f and 1f. configurable undervoltage lockout figure 1 shows how to configure an undervoltage lock - out (uvlo) for the ltm8049 . typically, uvlo is used in situations where the input supply is current-limited, has a relatively high sour ce resistance, or ramps up/down slowly. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current-limit or latch low under low source voltage conditions. uvlo prevents the regulator from operating at source voltages where these problems might occur. applications information the run pin has a voltage hysteresis with typical thresh - olds of 1.31v (rising) and 1.27v (falling). resistor r uvlo2 is optional. r uvlo2 can be included to reduce the overall uvlo voltage variation caused by variations in the run pin current (see the electrical characteristics). a good choice for r uvlo2 is 10k + 1%. after choosing a value for r uvlo2 , r uvlo1 can be determined from either of the following: r uvlo1 = v in(rising) C 1.31v 1.32v r uvlo2 + 12.1a or r uvlo1 = v in(falling) C 1.27v 1.29v r uvlo2 + 11.6a where v in(rising) and v in(falling) are the v in threshold voltages when rising or falling respectively. for example, to disable the ltm8049 for v in voltages below 3.5v using the single resistor configuration, choose: r uvlo1 = 3.5v C 1.27v 1.29v + 11.6a ? 191k to activate the ltm8049 for v in greater than 4.5v using the two resistor configuration, choose r uvlo2 = 10k and: r uvlo1 = 4.5v C 1.31v 1.32v 10k + 12.1a ? 22.1k internal undervoltage lockout the ltm8049 monitors the v in supply voltage in case v in drops below a minimum operating level (typically about 2.3v). when v in is detected low, the power switch is deactivated, and while sufficient v in voltage persists, the soft-start capacitor is discharged. after v in is sufficiently high, the ltm8049 will reactivate and the soft-start capaci - tor will begin charging. the run pin sinks 12.1a at the 1.31v rising threshold voltage and about 11.6a at the 1.27v falling threshold. this makes it easy to set up an input voltage uvlo thresh - old with just a single resistor. for a desired v in threshold, choose r uvlo1 using the equation: r uvlo1 = v in C 1.31v 12.1a figure 1. the run pin may be used to implement an accurate uvlo + ? lt m8049 8049fa 1.31v 12.3a at 1.31v gnd ltm8049 active/ lockout 8049 f01 r uvlo1 r uvlo2 (optional) v in v in run
13 for more information www.linear.com/ltm8049 applications information frequency foldback the frequency foldback function reduces the switching frequency for that channel when the output is about 15% below the target regulation point. this feature lowers the operating frequency, thus controlling the maximum output current during start-up. when the fbx voltage is pulled above the above mentioned range in a positive output volt - age application, the switching frequency for that channel runs that the rate set by the r t resistor value. note that the maximum output current at start-up is a function of many variables including load profile, output capacitance, target v out , v in , switching frequency, so the user must evaluate the performance of the ltm8049 to ensure that it properly powers up its load. thermal shutdown if the part is too hot, the ltm8049 engages its thermal shutdown and terminates switching and discharges the soft-start capacitor. when the part has cooled, the part auto - matically restarts. this thermal shutdown is set to engage at temperatures above the 125 c absolute maximum internal operating rating to ensure that it does not interfere with functionality in the specified operating range. this means that internal temperatures will exceed the 125c absolute maximum rating when the overtemperature protection is active, possibly impairing the devices reliability. pcb layout most of the headaches associated with pcb layout have been alleviated or even eliminated by the high level of integration of the ltm8049. the ltm8049 is neverthe - less a switching power supply, and care must be taken to minimize emi and ensure proper operation. even with the high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. see figure 2 for a suggested layout. ensure that the grounding and heat-sinking are acceptable. a few rules to keep in mind are: 1. place the r fbx and r t resistors as close as possible to their respective pins. 2. place the c in capacitor as close as possible to the v in and gnd connection of the ltm8049. 3. place the c out capacitor as close as possible to the v out and gnd connection of the ltm8049. figure 2. layout showing suggested external components, gnd plane and thermal vias 8049 f02 thermal/gnd vias v in2 v in1 v out1 (positive output) v out2 (negative output) gnd gnd gnd gnd share2 share1 ss1 ss2 run2 run1 sync1 sync2 rt1 rt2 pg2 pg1 fbx1 fbx2 clkout1 clkout2 gnd c in1 c in2 c out1 c out2 lt m8049 8049fa
14 for more information www.linear.com/ltm8049 applications information 4. place the c in and c out capacitors such that their ground current flow directly adjacent or underneath the ltm8049. 5. connect all of the gnd connections to as large a copper pour or plane area as possible on the top layer . avoid breaking the ground connection between the external components and the ltm8049. 6. use vias to connect the gnd copper area to the board s internal ground planes. liberally distribute these gnd vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. pay attention to the location and density of the thermal vias in figure 2. the ltm8049 can benefit from the heat-sinking afforded by vias that connect to internal gnd planes at these locations, due to their proximity to internal power handling components. the optimum number of thermal vias depends upon the printed circuit board design. for example, a board might use very small via holes. it should employ more thermal vias than a board that uses larger holes. hot-plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of ltm8049 . however, these capacitors can cause problems if the ltm8049 is plugged into a live input supply (see application note 88 for a complete dis - cussion). the low loss ceramic capacitor combined with stray inductance in series with the power sour ce forms an underdamped tank circuit, and the voltage at the v in pin of the ltm8049 can ring to more than twice the nominal input voltage, possibly exceeding the ltm8049 s rating and damaging the part. if the input supply is poorly controlled or the user will be plugging the ltm8049 into an energized supply, the input network should be designed to prevent this overshoot. this can be accomplished by installing a small resistor in series to v in , but the most popular method of controlling input voltage overshoot is to add an electrolytic bulk capacitor to the v in net. this capacitor s relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. the extra capacitor improves low frequency ripple filtering and can slightly improve the ef - ficiency of the circuit, though it is physically large. thermal considerations the lt m8049 output current may need to be derated if it is required to operate in a high ambient temperature or deliver a large amount of continuous power. the amount of current derating is dependent upon the input voltage, output power and ambient temperature. the temperature rise curves given in the typical performance character - istics section can be used as a guide. these curves were generated by a ltm8049 mounted to a 58cm 2 4- layer fr4 printed circuit board. boards of other sizes and layer count can exhibit different thermal behavior, so it is incumbent upon the user to verify proper operation over the intended system s line, load and environmental operating conditions. the thermal resistance numbers listed in page 2 of the data sheet are based on modeling the module package mounted on a test board specified per je sd51 -9 (test boards for area array surface mount package thermal measurements). the thermal coefficients provided in this page are based on jesd 51- 12 (guidelines for reporting and using electronic package thermal information). for increased accuracy and fidelity to the actual application, many designers use fea to predict thermal performance. to that end, page 2 of the data sheet typically gives four thermal coefficients: ja : thermal resistance from junction to ambient jcbottom : thermal resistance from junction to the bottom of the product case jctop : thermal resistance from junction to top of the product case jb : thermal resistance from junction to the printed circuit board. while the meaning of each of these coefficients may seem to be intuitive, jedec has defined each to avoid confusion and inconsistency. these definitions are given in jesd 51-12, and are quoted or paraphrased below: ja is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as lt m8049 8049fa
15 for more information www.linear.com/ltm8049 applications information still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. jcbottom is the thermal resistance between the junction and bottom of the package with all of the component power dissipation flowing through the bottom of the package. in the typical module converter, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions don t generally match the users application. jctop is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module converter are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junc - tion to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. jb is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module converter and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. given these definitions, it should now be apparent that none of these thermal coefficients reflects an actual physical operating condition of a module converter. thus, none of them can be individually used to accurately predict the thermal performance of the product. likewise, it would be inappropriate to attempt to use any one coefficient to correlate to the junction temperature vs load graphs given in the products data sheet. the only appropriate way to use the coefficients is when running a detailed thermal analysis, such as fea, which considers all of the thermal resistances simultaneously. a graphical representation of these thermal resistances is given in figure 3. the blue resistances are contained within the module converter, and the green are outside. the die temperature of the ltm8049 must be lower than the maximum rating of 125c, so care should be taken in the layout of the circuit to ensure good heat sinking of the ltm8049. the bulk of the heat flow out of the ltm8049 is through the bottom of the module converter and the bga pads into the printed circuit board. consequently a poor printed circuit board design can cause excessive heating, resulting in impaired performance or reliability. please refer to the pcb layout section for printed circuit board design suggestions. 8049 f03 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance figure 3. graphical representation of jesd51-12 thermal coefficients lt m8049 8049fa
16 for more information www.linear.com/ltm8049 typical applications 5v converter parallel 8v outputs for increased current maximum load current vs v in maximum load current vs v in lt m8049 8049fa 107k 750khz v in 2.7v to 15v v out1 5v v out2 ?5v 4.7f 2 47f 147f sync2 clkout1 fbx1 ltm8049 rt2 107k 750khz 60.4k v out2p v out2n v in2 run2 pins not used: ss1, ss2, pg1, pg2, clkout2, share1, share2 sync1 fbx2 45.3k ltm8049 82.5k 8049 ta03a v out1p v out1n v in1 run1 sync1 rt1 80.6k 1mhz 8049 ta02a v in 2.7v to 20v v out 8v 47f sync2 clkout1 share2 share1 fbx1 rt2 80.6k 1mhz v out1p 82.5k v out2p v out2n v in2 run2 pins not used: ss1, ss2, pg1, pg2, clkout2 fbx2 4.7f 2 v in (v) 0 v out1n 5 10 15 0 0.5 1.0 1.5 2.0 load current (a) 8049 ta02b v in1 v in (v) 0 5 10 15 20 0.5 1.5 2.5 3.5 run1 load current (a) 8049 ta03b rt1
17 for more information www.linear.com/ltm8049 pin assignment table (arranged by pin number) package description package photo pin name pin name pin name pin name pin name pin name a1 v out1p b1 v out1p c1 fbx1 d1 v out1n e1 v out1n f1 gnd a2 v out1p b2 v out1p c2 v out1n d2 v out1n e2 v out1n f2 gnd a3 gnd b3 gnd c3 gnd d3 gnd e3 gnd f3 share1 a4 gnd b4 gnd c4 gnd d4 gnd e4 gnd f4 share2 a5 v in1 b5 gnd c5 gnd d5 gnd e5 gnd f5 gnd a6 v in1 b6 gnd c6 gnd d6 p g1 e6 clkout1 f6 gnd a7 v in1 b7 ru n1 c7 s s1 d7 sy nc1 e7 rt1 f7 gnd pin name pin name pin name pin name pin name g1 v out2n h1 v out2n j1 fbx2 k1 v out2p l1 v out2p g2 v out2n h2 v out2n j2 v out2n k2 v out2p l2 v out2p g3 gnd h3 gnd j3 gnd k3 gnd l3 gnd g4 gnd h4 gnd j4 gnd k4 gnd l4 gnd g5 gnd h5 gnd j5 gnd k5 gnd l5 v in2 g6 clkout2 h6 p g2 j6 gnd k6 gnd l6 v in2 g7 rt2 h7 sy nc2 j7 s s2 k7 ru n2 l7 v in2 lt m8049 8049fa
18 for more information www.linear.com/ltm8049 package description please refer to http://www.linear.com/product/ltm8049#packaging for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z bga package 77-lead (15.00mm 9.00mm 2.42mm) (reference ltc dwg# 05-08-1964 rev b) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (77 places) a detail b package side view m x yzddd m zeee a2 d e bga 77 0517 rev b tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module detail a package bottom view 3 see notes a b c d e f g h j k l pin 1 e b f g 7 6 5 4 3 2 1 suggested pcb layout top view 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 0.025 ? 77x 6 see notes 5. primary datum -z- is seating plane 6 package row and column labeling may vary among module products. review each package layout carefully ! z detail b substrate a1 ccc z z // bbb z h2 h1 b1 mold cap symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 2.22 0.50 1.72 0.60 0.60 0.27 1.45 nom 2.42 0.60 1.82 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.32 1.50 max 2.62 0.70 1.92 0.90 0.66 0.37 1.55 0.15 0.10 0.20 0.30 0.15 total number of balls: 77 dimensions notes ball ht ball dimension pad dimension substrate thk mold cap ht lt m8049 8049fa
19 for more information www.linear.com/ltm8049 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. revision history rev date description page number a 12/17 added snpb bga package 1, 2 lt m8049 8049fa
20 for more information www.linear.com/ltm8049 lt 1217 rev a ? printed in usa www.linear.com/ltm8049 ? analog devices, inc. 2016 related parts typical application design resources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation t ools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products sear ch 1. sort table of products by parameters and download the result as a spread sheet. 2. sear ch using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management analog devices family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. parallel outputs to increase C5v output current maximum load current vs v in part number description comment ltm8045 single. inverting or sepic module dc/dc convertor 2.8 v in 18v. 2.5v v out 15v. 6.25mm 11.25mm 4.92mm bga ltm8046 2kvac, 2.75w isolated dc/dc module converter 3.1v v in 31v, 1.8v v out 12v. 5v at 550ma from 24v in , 9mm 15mm 4.92mm bga lt m8047 725kvdc, 1.5w isolated dc/dc module converter 3.1v v in 32v, 2.5v v out 12v. 9mm 11.25mm 4.92mm bga ltm8048 725kvdc, 1.5w isolated dc/dc module converter with integrated ldo 3.1v v in 32v, 1.2v ldo v out 12v. 9mm 11.25mm 4.92mm bga ltm8067 2kvac, 2.25w isolated dc/dc module converter 2.8v v in 40v, 2.5v v out 24v. 9mm 11.25mm 4.92mm bga ltm8068 2kvac, 2.25w isolated dc/dc module converter with integrated ldo 2.8v v in 40v, 1.2v ldo v out 18v. 9mm 11.25mm 4.92mm bga ltm8023 36v in , 2a, step-down dc/dc module converter. can be used for inverting 3.6v v in 36v, 0.8v v out 10v. 9mm x 11.25mm x 2.82mm lga. 9mm x 11.25mm x 3.52mm bga lt m8053 40v in , 3.5a step-down dc/dc module regulator. can be used for inverting. 3.4v v in 40v. 0.97v v out 15v. 6.25mm x 9mm x 3.32mm bga. lt m8049 8049fa rt1 107k 750khz v in 2.7v to 15v v out ?5v 100f 2 sync2 clkout1 share2 share1 fbx1 ltm8049 rt2 107k 750khz 60.4k v out2p v out2n v in2 run2 pins not used: ss1, ss2, pg1, pg2, clkout2 fbx2 4.7f 2 60.4k v in (v) 0 5 10 15 20 0 1 2 3 8049 ta04a 4 load current (a) 8049 ta04b v out1p v out1n v in1 run1 sync1

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